Christopher SEKIYA wileyc@rezrov.net said;

> I've narrowed the problem down a bit: csh invokes something in libc that will
> panic a machine with a r4k-style cache (Manuel's response indicates that r5k
> will just dump core).

Just out of curiosities.  Is there a product variation in r5k Indy/o2 to have/not to
have L2 cache?  The number of L2 equipped MIPS CPU is small these days, then
malfunction of cache handling is rather hard to catch.

Toru Nishimura/ALKYL Technology