Subject: Re: Figures to explain MIPS cache
To: None <port-mips@netbsd.org>
From: Toru Nishimura <locore32@gaea.ocn.ne.jp>
List: port-mips
Date: 12/21/2003 21:52:19
Simon Burge said;

> Note that from NetBSD's point of view, the Au1000 cache is fully
> coherent, even when fetching in to the instruction cache.  Thus
> there is no need for any specific cache handling at all.

It's interesting. What's the difference between the IDT and Au?

Toru Nishimura/ALKYL Technology