Wanabee an encouraging "good" guy, I made figures to explain
MIPS VIPT cache for three processors; R4600, R5000 and
RM7000.  It's available at;

    http://www.alkyltechnology.com/files/MIPScachefigure1.pdf

Those three were selected for ease to draw.  I have unfinished R4000
case.  It's complicated because;
- L1 line size is configurable,
- L2 line size is also configurable,
- line sizes of L1 and L2 do not match,
- L2 cache tag is _very distinctive_ feature to store "the portion of vAddr
to select L1 cache line index."

Figures of Toshiba TX39 and 49 should be added easily and helpful.
Please pay attention about RM7000 case.   Since the L1 is 16KB/4way,
the L1 index is VA11-5, which is actually PA11-5, then RM7000 is 
"effective-PIPT" processor.

Toru Nishimura/ALKYL Technology