Subject: Re: Removing MIPS3_L2CACHE_ABSE
To: None <port-mips@netbsd.org>
From: Toru Nishimura <locore32@gaea.ocn.ne.jp>
List: port-mips
Date: 12/13/2003 15:14:09
It seems I must be more informative.  My suggestion was it'd be
more consistent to determine "if-the-cache-is-VIPT" there.

The intent of original if-clause looks like "if-not-VCE-available" then
"wbinv()".  That  means L2-equipped R4000 case was expected to
"solve" VA condition which zero_page() just made by VCED handler
soon after.  Ok, that's good for patch work, however, it's a mistake
for zero_page() to make VA condition after all.

Let's face the fact.  Only L2-equipped R4000 is capable of emitting
VCE.   Please look at how R4000 L2-cache _tag_ is designed (PDF
is available online), and draw figures about how virtual address is
decomposed to use TLB/cache.  And then please imagine the reason
why no other VIPT MIPS has VCE.

The main drawback of VIPT cache is people don't have good knowledge
about it even though it's a best fit cache for UNIX-like OS and the world
is dominated by PIPT processors.  The book explains the details.  Then,
you could grasp wisdom of how bad VIVT cache is and how smart VIPT
cache is.  I guess ARM camp finally got the idea by changing their VIVT
cache into VIPT.

Toru Nishimura/ALKYL Technology