All,

Tsutsui-san (I think) committed changes to arch/mips/mips/pmap.c a while back
that rendered MIPS3_L2CACHE_ABSENT redundant -- all code wrapped within the
conditional is in turn wrapped in a conditional testing whether
mips_sdcache_line_size is zero.

The below patch removes the offending #ifdefs.  If there is no objection, I'd
like to commit this next Monday.

-- Chris
	GPG key FEB9DE7F (91AF 4534 4529 4BCC 31A5  938E 023E EEFB FEB9 DE7F)


Index: pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/pmap.c,v
retrieving revision 1.153
diff -u -r1.153 pmap.c
--- pmap.c	1 Nov 2003 14:48:16 -0000	1.153
+++ pmap.c	12 Dec 2003 02:02:13 -0000
@@ -264,7 +264,6 @@
 void mips_dump_segtab(struct proc *);
 #endif
 
-#if defined(MIPS3_L2CACHE_ABSENT)
 /*
  * Flush virtual addresses associated with a given physical address
  */
@@ -288,7 +287,6 @@
 	}
 #endif
 }
-#endif	/* MIPS3_L2CACHE_ABSENT */
 
 /*
  *	Bootstrap the system enough to run with virtual memory.
@@ -1583,7 +1581,7 @@
 
 	mips_pagezero((caddr_t)MIPS_PHYS_TO_KSEG0(phys));
 
-#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT)	/* XXX mmu XXX */
+#if defined(MIPS3_PLUS)	/* XXX mmu XXX */
 	/*
 	 * If we have a virtually-indexed, physically-tagged WB cache,
 	 * and no L2 cache to warn of aliased mappings,	we must force a
@@ -1595,7 +1593,7 @@
 	 */
 	if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0)
 		mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
-#endif	/* MIPS3_PLUS && MIPS3_L2CACHE_ABSENT */
+#endif	/* MIPS3_PLUS */
 }
 
 /*
@@ -1616,7 +1614,7 @@
 		printf("pmap_copy_page(%lx) dst nonphys\n", (u_long)dst);
 #endif
 
-#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT)	/* XXX mmu XXX */
+#if defined(MIPS3_PLUS) /* XXX mmu XXX */
 	/*
 	 * If we have a virtually-indexed, physically-tagged cache,
 	 * and no L2 cache to warn of aliased mappings, we must force an
@@ -1635,12 +1633,12 @@
 		mips_flushcache_allpvh(src);
 /*		mips_flushcache_allpvh(dst); */
 	}
-#endif	/* MIPS3_PLUS && MIPS3_L2CACHE_ABSENT */
+#endif	/* MIPS3_PLUS */
 
 	mips_pagecopy((caddr_t)MIPS_PHYS_TO_KSEG0(dst),
 		      (caddr_t)MIPS_PHYS_TO_KSEG0(src));
 
-#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT)	/* XXX mmu XXX */
+#if defined(MIPS3_PLUS) /* XXX mmu XXX */
 	/*
 	 * If we have a virtually-indexed, physically-tagged WB cache,
 	 * and no L2 cache to warn of aliased mappings,	we must force a
@@ -1656,7 +1654,7 @@
 		mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(src), NBPG);
 		mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(dst), NBPG);
 	}
-#endif	/* MIPS3_PLUS && MIPS3_L2CACHE_ABSENT */
+#endif	/* MIPS3_PLUS */
 }
 
 /*
@@ -1882,7 +1880,7 @@
 		pv->pv_pmap = pmap;
 		pv->pv_next = NULL;
 	} else {
-#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT)	/* XXX mmu XXX */
+#if defined(MIPS3_PLUS) /* XXX mmu XXX */
 		if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0) {
 			/*
 			 * There is at least one other VA mapping this page.
@@ -1935,7 +1933,7 @@
 			}
 #endif	/* !MIPS3_NO_PV_UNCACHED */
 		}
-#endif /* MIPS3_PLUS && MIPS3_L2CACHE_ABSENT */
+#endif /* MIPS3_PLUS */
 
 		/*
 		 * There is at least one other VA mapping this page.