manu@netbsd.org (Emmanuel Dreyfus) said;

> While fixing COMPAT_IRIX, I discovered I still havd this local patch:
> ...
> ...restoring CP0 SR value...
> ...
> Anyone want to do something with that? I believe it is related to the
> following mips only problem (there is a PR about this, but I can't find
> it anymore)

Your code looks reasonable (somehow) to me, however, I have severals to
say;
- the small program you provided is running very long time on stock i386
1.6-RELEASE eating CPU cycle, so your asserting is in doubt.
- there is "instruction hazard issue" immediately after load instruction.
This is a processor design issue peculiar to MIPS.  The processor(s) you use
may not make any trouble for the instruction sequence in particular, but
neglecting
load delay issue sets fires to the entire MIPS integrality.  You're warned.
- Please, don't be quick to fix/change/improve the suspicious code segments
before grasping what the matter really is.  The code we have now is known
bogus/dirty/hacky, and fortunately working.  It must be made clean to go
further, with large efforts to avoid spoiling NetBSD/mips.  Ask before any
change when something looks wrong.

Toru Nishimura/ALKYL Technology