Izumi Tsutsui reported me a set of interesting figures.  R4000/4400 allows
variety of cache line size configured inside a system.  Primary cache line size is
the choice of 16B or 32B, while off-chip external cache line size is the choice from
16B, 32B, 64B or128B.  The size combination is defined by hardware circuit,
and kernel can not choose inconsistent values.

VCE is a way to make the chip flexible about memory circuit design.  I guess it
was the intent of R4000/4400 designers.  They even wanted to have an option to
allow separated L2 I$ and D$ in parallel.  However, today's industry trend settled
down to unified L2 cache and a single line size which is consistent across multiple
level caches.  R10000 L2 cache tag has similar design to R4000/4400, but the
chip does VCE matter in hardware.  Hence, VCE handler is solely for R4000/4400.

Toru Nishimura/ALKYL Technology
------------
NEC Express5800/240 R4400 EISA
cpu0 at mainbus0: MIPS R4400 CPU (0x460) Rev. 6.0 with MIPS R4010 FPC Rev. 0.0
cpu0: 16KB/32B direct-mapped L1 Instruction cache, 48 TLB entries
cpu0: 16KB/32B direct-mapped write-back L1 Data cache
cpu0: 2048KB/64B direct-mapped write-back L2 Unified cache

NEC Express 5800/230 R4400 PCI
cpu0 at mainbus0: MIPS R4400 CPU (0x460) Rev. 6.0 with MIPS R4010 FPC Rev. 0.0
cpu0: 16KB/32B direct-mapped L1 Instruction cache, 48 TLB entries
cpu0: 16KB/32B direct-mapped write-back L1 Data cache
cpu0: 1024KB/64B direct-mapped write-back L2 Unified cache

MIPS Magnum
cpu0 at mainbus0: MIPS R4000 CPU (0x430) Rev. 3.0 with MIPS R4010 FPC Rev. 0.0
cpu0: L1 cache: 8KB/16B instruction, 8KB/16B data, direct mapped
cpu0: L2 cache: 1024KB/16B mixed, no snooping

DECstation 5000/260 (3MAXPLUS)
cpu0 at mainbus0: MIPS R4400 CPU (0x440) Rev. 4.0 with MIPS R4010 FPC Rev. 0.0
cpu0: 16KB/16B direct-mapped L1 Instruction cache, 48 TLB entries
cpu0: 16KB/16B direct-mapped write-back L1 Data cache
cpu0: 1024KB/32B direct-mapped write-back L2 Unified cache

SONY NET WORK STATION, Model NWS-5000, Machine ID #14668
cpu0 at mainbus0: MIPS R4400 CPU (0x450) Rev. 5.0 with MIPS R4010 FPC Rev. 0.0
cpu0: 16KB/16B direct-mapped L1 Instruction cache, 48 TLB entries
cpu0: 16KB/16B direct-mapped write-back L1 Data cache
cpu0: 1024KB/64B direct-mapped write-back L2 Unified cache

SGI-IP22 [SGI, 690a6af3]
cpu0 at mainbus0: MIPS R4400 CPU (0x460) Rev. 6.0 with MIPS R4010 FPC Rev. 0.0
cpu0: 16KB/16B direct-mapped L1 Instruction cache, 48 TLB entries
cpu0: 16KB/16B direct-mapped write-back L1 Data cache
cpu0: 2048KB/128B direct-mapped write-back L2 Unified cache
----