Rafal Boni <rafal@attbi.com> asked;

> So here are my questions:
>  * Is there something better we can do than always flushing
>    caches in pmap_copy_page and pmap_zero_page?

The implementation is s*ck.   Rather better to map reserved
VADDR on-the-fly like as some of other NetBSD ports do.
It'd depend on particular CPU characteristics if writethru
better performs than writeback-then-flush scheme.
 
>  * Are there things we should be thinking about to actively
>    avoid relying on VCE support, or is it simply not worth
>    the effort?

???  Virtual coherency exception does matter for the processor
whose L2 cache line size is larger than L1, doesn't it?
Recent processors allow to bypass L1 or L2 when a specific
CCA is assigned, but it's another story.

>  * On a related note, is it worth tuning some of the pmap
>    code for situations where we don't have VCE support?
>   (I don't know which other MIPS CPUs have this issue..
>    Maybe the R4600 as well?)
>  * Is there a reason for the MIPS3_L2CACHE_ABSENT option?
>    Should it be nuked?

Yes, it's very wrong to exist.

Toru Nishimura/ALKYL Technology