Subject: R5k vs. MIPS pmap: or dealing with CPUs that don't do VCE
To: None <firstname.lastname@example.org>
From: Rafal Boni <email@example.com>
Date: 12/17/2002 16:29:21
Starting with Chris Sekiya's latest O2 code, I've now gotten my
O2 with R5000SC booting with the L2 cache enabled. However, it
turns out that the R5k does not do VCE, which means I had to hack
up my copy of the MIPS pmap to always do the extra cache flushes
in pmap_zero_page() and pmap_copy_page() as if the system did not
actually have any L2 cache.
Since I'm not too familiar with the MIPS pmap, I thought I'd ask
here for thoughts on what we can do to make the pmap code deal
with this in a somewhat better way. Also, it seems strange to
me that the code to do the extra cache flushes is surrponded by
an `#ifdef MIPS3_L2CACHE_ABSENT'; this option is present in the
sgimips GENERIC, which explains why it did work on the L2-less
R5000PC or the R5000SC with L2 cache disabled in CP0_CONFIG, but
why do we require an option to support L2-cache-less sytems?
So here are my questions:
* Is there something better we can do than always flushing
caches in pmap_copy_page and pmap_zero_page?
* Are there things we should be thinking about to actively
avoid relying on VCE support, or is it simply not worth
* On a related note, is it worth tuning some of the pmap
code for situations where we don't have VCE support?
(I don't know which other MIPS CPUs have this issue..
Maybe the R4600 as well?)
* Is there a reason for the MIPS3_L2CACHE_ABSENT option?
Should it be nuked?
Any thoughts on this appreciated; as I mentioned above, I'm a true
novice when it comes to the pmap, so try to not aim responses too
Rafal Boni firstname.lastname@example.org
We are all worms. But I do believe I am a glowworm. -- Winston Churchill