>>>>> "Toru" == Toru Nishimura <locore32@gaea.ocn.ne.jp> writes:

 Toru> Folks, mipsX_subr.S contains _MFC0/_MTC0 mnemonics to handle
 Toru> EntryLo[0|1] registers.  Because standard MIPS 36bit physical
 Toru> address is compactly stored inside 32bit EntryLo[0|1]
 Toru> registers, it makes little sense to use 64bit CP0 instruction
 Toru> for them as long as we will not venture the extended potential
 Toru> of R1x000 processors.  I think rather better to keep PTE in
 Toru> 32bit size and change mipsX_subr.S so-so. Comments?

What about MIPS processors with 40-bit physical addresses?  For those
the PFN expands into the upper 32 bits, I assume.  (The MIPS PRA spec
doesn't show it in the diagram though the text implies it.)

    paul