Here is an explanation of CONTEXT register design intent.

CONTEXT register is to maintain PTEs as a single linear
array in KVA, specifically somewhere in KSEG2.
Upon TLB miss condition,  processor fills CONTEXT register
with a ptr value to point the PTE to refill.   PTEbase field
of the register is the base (virtual) address of PTE array.
The remaining low order field is an index to choose PTE,
which is calculated by faulting VADDR.   MIPS processor
document does not mention clearly about such the PTE
arrangement, and some OSes, including NetBSD/mips we
have now, do not make any use of the register.  Digital's
Alpha processor adheres the linear PTE approach and calls
it as VPT (virtual PT).  It might be a concern that PTE array
layout itself consumes TLB entries, however, a single TLB
entry brings 4MB range coverage at a time, and it's not a bad
deal given the spatial locality nature of address reference pattern.

MIPS processor leaves unspecified how OS manages
such the linear PTE array in KVA.  It's a responsibility
of software implementation.   Technically, it matters
the way how software responds to TLB miss on PTE
lookup.  This is a double (nested) fault case.  The faulting
address must be resolved with a TLB entry to hold
the matching chunk of 1024 PTEs before the initial
TLB refill handler is resumed.

It's worth of mentioning that MIPS TLB does allow to hold
an invalid TLB entry inside.   The intent is a simplicity of TLB
refill logic, which is ok to unaware of loading invalid PTE
to it.   MIPS processor posts TLB invalid exception for
NV (not valid) TLB entry and leaves the rest of work to OS.
It's an OS responsibility to analyze the TLB invalid condition
distinguishing it for genuine illegal address access, demand page
loading from file system, zero-fill-on-demand anonymous store,
page reclaim from swap backing store, or plain stack expansion, 

Toru Nishimura/ALKYL Technology