Paul Koning wrote:

>instruction would let you avoid the cacheline fill when you're writing
>a full cacheline; PREF only lets you move that fill earlier in time.
>If you're memory-bound, PREF may produce a small performance
>improvement, but CACHE will give a significantly larger improvement.
>
>Unfortunately the create dirty exclusive operation is a
>platform-dependent operation.  Some MIPS processors have it, some
>(including some very recent ones) do not.
>  
>
In MIPS32 and MIPS64 compliant processors the "pref" instruction with 
code 30 is defined as "prepare for store" with the following description:

    PrepareForStore

    Use: Prepare the cache for writing an entire line, without the
    overhead involved in filling the line from memory.

    Action: If the reference hits in the cache, no action is taken. If
    the reference misses in the cache, a line is selected for
    replacement, any valid and dirty victim is written back to memory,
    the entire line is filled with zero data, and the state of the line
    is marked as valid and dirty.

The other advantage of the pref instruction is that it can be included 
in user code, whereas the cache instruction is only available to the kernel.

Nigel

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