Simon Burge simonb@wasabisystems.com wrote;

> Could folks that know for sure that various models of MIPS cpus _don't_
> support the LL & SC instructions please update the table we have that
> describes CPU capabilities?  This involves adding the CPU_MIPS_NO_LLSC
> flag in the cputab in sys/arch/mips/mips/mips_machdep.c.

- I can not find out any reference mentioning TX39 core has LL/SC
extension inside.  (the R3000A variant does have cache instruction)
- Toshiba's TX49 core document (dated Sept. 1998) describes LL/SC and
LLD/SCD instructions in complete instruction coverage list.   However,
I can see an embarrassing statement in TMPR4955/4956 tentative document
(dated 20-Oct.-1999);

"TX4956 and TX4955 are not supporting the Load-Linked/Store-Conditional
instruction sequence."

The document does not explain what would happen when these TX49
processors try to run LL/SC instructions.

Toru Nishimura/ALKYL Technology