Mark Simmons <mds@gbnet.net> wrote;

> Just a quick point to ponder, I have two SGI PowerSeries machines in my
> living room each with 6+ R3K cpu's. IIRC they were the first SMP Unix
> boxes in the general market (model-wise, not these specific boxes),
> and under IRIX5.3 did a sterling job.

In a book "UNIX Internals", the author mentions (pp.501-502) about
the machine in the context of how TLB shootdown is done.   He marks
a reference to USENIX paper (Translation Lookaside Buffer
synchronization in a Multiprocessor System, 1988 Winter USENIX)
I assume the TLBpid management is the same as what NetBSD/alpha
does with inter-processor interrupt.

As side note, there is LL/SC-less post-R3K MIPS processor
besides of Vr4100 and the number of such beasts might grow.
I can't figure out the reason to remove it since modern MIPS
processors are expected to use for embeded products of
"pretty light-weight multi-threading" systems...

Toru Nishimura