locore32@gaea.ocn.ne.jp ("Toru Nishimura") writes:
> > I notice in your diff you say:
> >
> > +# Invalid combinations are     
> > +#  * MIPS1_3000 && (MIPS1_3900 || MIPS1_3920)
> > +#  * (MIPS3_4000 || MIPS3_4600 || MIPS3_5000) && MIPS3_4100
> > +#  * (MIPS3_4000 || MIPS3_4600 || MIPS3_5000) && MIPS3_5900
> > +#  * MIPS3_4100 && MIPS3_5900
> >
> > Why are these actually invalid combinations?  (that seems bogus...)
> 
> How about categorize and collerate the functional aspect of CPU designs
> instead of patch works to fill holes like that?
> 
> - TLB
>     R3KTLB or R4KTLB (possibly R4KTLB64 for LP64)
> - cache 
>     R3KCACHE, R4KCACHE (, R5KCACHE) or TX39CACHE ...
> - FP registers
>     FPPAIRED32 (thirty-two 32bit), FPDOUBLE (thirty-two 64bit) or FPSINGLE (sorta)
> - others necessary...

Err, uh, users _definitely_ shouldn't have to think about _these_ in
their config files.

While there's some chance that they'll know what kind of CPU is in
their box, it seems ... unlikely that they'll know enough about its
cp0 to intelligently pick among these...


cgd