uch@vnop.net ("UCHIYAMA Yasushi") writes:
> I prefer to specify CPU architecture rather than ISA. Because
> nowadays instruction set architecture don't reflect its cache
> implementation.

Actually, these days more than ever (i.e., with MIPS32/MIPS64), ISA
and cache implementation (or at least, instructions used to access
them; the sizes etc., are variable but can be dtermined easily) to
hand in hand...  8-)



> Do you think about this patch? 
> ftp://ftp.netbsd.org/pub/NetBSD/misc/uch/mips.cache.conf.patch
> And this patch reduce kernel size.(don't link unneeded code)
> it is important for small memory machines.

This type of thing really is something where you'd like a library
which causes stuff to be pulled in only if needed, or some other good
mechanism to derive cache options from e.g. machine types which are
selected.

People shouldn't need to know what kind of CPU is actually in their
machine to configure a kernel for it, esp. when there are as many
possible CPU variants as there are in the MIPS world.  It should be
derived from machine type.

This is made worse by the fact that in fact, even if they know what
CPU is in their machine, often they _cannot_ specify it.
e.g. MIPS1_2000.  No, that's MIPS1_3000, which includes R2000
support.


I notice in your diff you say:

+# Invalid combinations are     
+#  * MIPS1_3000 && (MIPS1_3900 || MIPS1_3920)
+#  * (MIPS3_4000 || MIPS3_4600 || MIPS3_5000) && MIPS3_4100
+#  * (MIPS3_4000 || MIPS3_4600 || MIPS3_5000) && MIPS3_5900
+#  * MIPS3_4100 && MIPS3_5900

Why are these actually invalid combinations?  (that seems bogus...)





chris