In article <20011118100641.E8922@dr-evil.shagadelic.org>
thorpej@wasabisystems.com wrote:

> BTW, what's the line size of our L2 cache?  128 bytes?  We could probably
> squeeze some more out by writing 128-byte optimized L2 cache ops (which
> unroll the loop somewhat).

I think the line size of L2 cache is machine-dependent:

arc (MIPS Magnum):
> cpu0: L2 cache: 1024KB/16B mixed, no snooping

arc (NEC JC94)
> cpu0: L2 cache: 1024KB/64B mixed, no snooping

newsmips (NWS-5000):
> cpu0: L2 cache: 1024KB/64B mixed, no snooping

pmax (5000/260):
> cpu0: L2 cache: 1024KB/32B mixed, no snooping

sgimips (IP22):
> cpu0: L2 cache: 1024KB/128B mixed, no snooping
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Izumi Tsutsui
tsutsui@ceres.dti.ne.jp