[ catching up on the mailing lists]

cgd@broadcom.com wrote:

> locore32@gaea.ocn.ne.jp ("Toru Nishimura") writes:
> > One point which affects NetBSD/mips in general.  It would be better to
> > avoid dmtc0/dmfc0 and keep other dXXX arithmetics minimal in order to
> > make entire code sane and less painfull for MIPS32 processor.  64bit pointer
> > is hardly justified before NetBSD/mips64.   And MIPS32 can be considered
> > as a "norm case" keeping other type processor compatiblities in mind.
> 
> Uh, what would you currently eliminate, from the uses of dm?c0 ops.
> 
> I imagine some of the TLB HI/LO, etc. uses could be removed (not sure
> if it'd really be portable, though -- i'd have to check my MIPS64
> specs, and i don't know that it's worth it to me to spend my time on
> it.  also don't know what that'd do to e.g. phys addr size
> restrictions)...
> 
> some of the uses (e.g. the badvaddr, exception/error PC, etc.)
> wouldn't be _correct_ if you changed them to use just mfc0...
> 
> 
> If the goal is to abstract old-MIPS vs. MIPS32 vs. MIPS64, etc.,
> exception handlers, that's best done by... having different exception
> handlers, which aren't common code.  (Or, by creating a single set of
> code which can have the some instructions #defined as appropriate, and
> then gets included multiple times.)

I've got a chunk of code that does this that I'll be putting up for
review soon.  In some cases I we have to break out to different
exception handlers because of space limitations, in others I check the
"cpu_arch" variable (constrained by some #ifdef ugliness).

There's still much messiness however that I'd like to clean up (like
assumptions between what really is MIPS1, MIPS3, MIPS32 and MIPS64 and
what exactly implies 32bit vs 64bit).  I'm currently working with

	/* This test is ... rather bogus */
	#define CPUISMIPS3      ((cpu_arch & \
		(CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)

	/* And these aren't much better while the previous test exists as is... */
	#define CPUISMIPS32     ((cpu_arch & CPU_ARCH_MIPS32) != 0)
	#define CPUISMIPS64     ((cpu_arch & CPU_ARCH_MIPS64) != 0)
	#define CPUISMIPSNN     ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
	#if 0
	#define CPUIS64BITS     ((cpu_arch & \
		(CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0)
	#else
	/* XXX hack because MIPS32 implies MIP3 for now */
	#define CPUIS64BITS     (((cpu_arch & \
		(CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) && \
		(!(cpu_arch & CPU_ARCH_MIPS32)))
	#endif
	#endif /* run-time test */

in <mips/cpu.h> with is far from pretty (or correct).

One end goal is for it to be possible, for example, to have one
kernel that boots on all the MIPS Malta boards, and those can come
with MIPS-IV, MIPS32 and MIPS64 cpus.

Simon.
--
Simon Burge                            <simonb@wasabisystems.com>
NetBSD CDs, Support and Service:    http://www.wasabisystems.com/