Hi again,

Here's some changes to <mips/cpureg.h> so that the CP0 register names
can be used in C code as well as assembler.

I'll commit this in a day or three (after the weekend) if no one has any
problems with it.

Simon.
--
Simon Burge                            <simonb@wasabisystems.com>
NetBSD CDs, Support and Service:    http://www.wasabisystems.com/


Index: cpuregs.h
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/include/cpuregs.h,v
retrieving revision 1.46
diff -d -p -u -r1.46 cpuregs.h
--- cpuregs.h	2001/08/17 07:53:33	1.46
+++ cpuregs.h	2001/10/05 05:14:11
@@ -409,53 +409,61 @@
  * 30	MIPS_COP_0_ERROR_PC	.636 Error EPC register.
  * 31	MIPS_COP_0_DESAVE	.... DESAVE JTAG register.
  */
-#define MIPS_COP_0_TLB_INDEX	$0
-#define MIPS_COP_0_TLB_RANDOM	$1
+
+#ifdef _LOCORE
+#include <sys/cdefs.h>
+#define	_(n)	__CONCAT($,n)
+#else
+#define	_(n)	n
+#endif
+
+#define MIPS_COP_0_TLB_INDEX	_(0)
+#define MIPS_COP_0_TLB_RANDOM	_(1)
 	/* Name and meaning of	TLB bits for $2 differ on r3k and r4k. */
 
-#define MIPS_COP_0_TLB_CONTEXT	$4
+#define MIPS_COP_0_TLB_CONTEXT	_(4)
 					/* $5 and $6 new with MIPS-III */
-#define MIPS_COP_0_BAD_VADDR	$8
-#define MIPS_COP_0_TLB_HI	$10
-#define MIPS_COP_0_STATUS_REG	$12
-#define MIPS_COP_0_CAUSE_REG	$13
-#define MIPS_COP_0_STATUS	$12
-#define MIPS_COP_0_CAUSE	$13
-#define MIPS_COP_0_EXC_PC	$14
-#define MIPS_COP_0_PRID		$15
+#define MIPS_COP_0_BAD_VADDR	_(8)
+#define MIPS_COP_0_TLB_HI	_(10)
+#define MIPS_COP_0_STATUS_REG	_(12)
+#define MIPS_COP_0_CAUSE_REG	_(13)
+#define MIPS_COP_0_STATUS	_(12)
+#define MIPS_COP_0_CAUSE	_(13)
+#define MIPS_COP_0_EXC_PC	_(14)
+#define MIPS_COP_0_PRID		_(15)
 
 
 /* MIPS-I */
-#define MIPS_COP_0_TLB_LOW	$2
+#define MIPS_COP_0_TLB_LOW	_(2)
 
 /* MIPS-III */
-#define MIPS_COP_0_TLB_LO0	$2
-#define MIPS_COP_0_TLB_LO1	$3
+#define MIPS_COP_0_TLB_LO0	_(2)
+#define MIPS_COP_0_TLB_LO1	_(3)
 
-#define MIPS_COP_0_TLB_PG_MASK	$5
-#define MIPS_COP_0_TLB_WIRED	$6
+#define MIPS_COP_0_TLB_PG_MASK	_(5)
+#define MIPS_COP_0_TLB_WIRED	_(6)
 
-#define MIPS_COP_0_COUNT	$9
-#define MIPS_COP_0_COMPARE	$11
+#define MIPS_COP_0_COUNT	_(9)
+#define MIPS_COP_0_COMPARE	_(11)
 
-#define MIPS_COP_0_CONFIG	$16
-#define MIPS_COP_0_LLADDR	$17
-#define MIPS_COP_0_WATCH_LO	$18
-#define MIPS_COP_0_WATCH_HI	$19
-#define MIPS_COP_0_TLB_XCONTEXT $20
-#define MIPS_COP_0_ECC		$26
-#define MIPS_COP_0_CACHE_ERR	$27
-#define MIPS_COP_0_TAG_LO	$28
-#define MIPS_COP_0_TAG_HI	$29
-#define MIPS_COP_0_ERROR_PC	$30
+#define MIPS_COP_0_CONFIG	_(16)
+#define MIPS_COP_0_LLADDR	_(17)
+#define MIPS_COP_0_WATCH_LO	_(18)
+#define MIPS_COP_0_WATCH_HI	_(19)
+#define MIPS_COP_0_TLB_XCONTEXT _(20)
+#define MIPS_COP_0_ECC		_(26)
+#define MIPS_COP_0_CACHE_ERR	_(27)
+#define MIPS_COP_0_TAG_LO	_(28)
+#define MIPS_COP_0_TAG_HI	_(29)
+#define MIPS_COP_0_ERROR_PC	_(30)
 
 /* MIPS32/64 */
-#define	MIPS_COP_0_DEBUG	$23
-#define	MIPS_COP_0_DEPC		$24
-#define	MIPS_COP_0_PERFCNT	$25
-#define	MIPS_COP_0_DATA_LO	$28
-#define	MIPS_COP_0_DATA_HI	$29
-#define	MIPS_COP_0_DESAVE	$31
+#define	MIPS_COP_0_DEBUG	_(23)
+#define	MIPS_COP_0_DEPC		_(24)
+#define	MIPS_COP_0_PERFCNT	_(25)
+#define	MIPS_COP_0_DATA_LO	_(28)
+#define	MIPS_COP_0_DATA_HI	_(29)
+#define	MIPS_COP_0_DESAVE	_(31)
 
 /*
  * Values for the code field in a break instruction.