Subject: pmap_procwr() for signal trampoline
To: None <email@example.com>
From: Toru Nishimura <firstname.lastname@example.org>
Date: 09/27/2001 11:07:26
The code fragment in pmap_procwr()::arch/mips/mips/pmap.c looks pretty
bogus although it seems to DTRT. The MI routine is supposedly to make
sure CPU will fetchs instruction sequence just written on user stack
for signal deliver. It's sorta 'instruction barrier' something, I
guess, anticipating R4000 nature of write-back cache. However, is it
_really_ worth doing such the thing in such the way after all?
Data points for discussion.
R3000 (mostly, besides of hybrid processor with cache op)
- physically-indexed (requires KSEG0 address to manipulate)
- virtually-indexed (ok for KSEG2 or KUSEG) with ASID
- direct-mapped or higher way set associatives