Toru Nishimura wrote:
> 
> An excerpt from mips/locore_mips3.S commit message;
> 
> | revision 1.58
> | date: 2000/10/24 03:23:19;  author: castor;  state: Exp;  lines: +20 -3
> | In mips3_TBIS(va) do not invalidate the other half of the JTLB entry if
> | the page is wired down.  Flushing both halves of a wired TLB entry resulted
> | in hangs when in programs called for and released kernel memory
> | soon after being invoked.  In particular, we see this when single-stepping
> | a process using GDB.
> 
> Isn't better (and conceptually consistent) for TBIS() to skip TLB
> invalidation if the target entry is wired down?

The problem is the UAREA is 8KB and depending on alignment can span 2
TLB entires.  We were seeing the wired entry on the first half and
an unrelated page get used on the second half.

Would it work of if TBIS skipped it?  The desired page really shouldn't
be wired, but just is.  It seems that has risks too.

The whole mess could be avoided if the UAREA was naturally aligned, at
least
on mips.  This is in MI code though.  We'd also gain another tlb entry
if
this were true.  That seems like the best fix.  I think there is newer
uvm code to allow this to happen with some optional MD macros.

jeffs

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