An excerpt from mips/locore_mips3.S commit message;

| revision 1.58
| date: 2000/10/24 03:23:19;  author: castor;  state: Exp;  lines: +20 -3
| In mips3_TBIS(va) do not invalidate the other half of the JTLB entry if
| the page is wired down.  Flushing both halves of a wired TLB entry resulted
| in hangs when in programs called for and released kernel memory
| soon after being invoked.  In particular, we see this when single-stepping
| a process using GDB.
|
| It would be better if we could arrange to use both halves of the TLB
| entry for the PCB, but for some reason we frequently end up with things
| on an odd page boundary.

USPACE hardwiring logic can be eliminated after all if there was the way
to obtain a consequetive 8KB chunk physical memory.  In that case, process's
USPACE would be managed by KSEG1 address just like proc0.

Tohru Nishimura