>> there is a small window that EXL bit takes 
>> effect since SR value is restored. So, if we simplely restore SR value
>> (i.e. sets both interrupt mask bits and the EXL bit at the same time), 
>> interrupt will be incorrectly enabled.
>
> Hairly...  How about this?

I learned it was necessary to read and understand See MIPS Run

	- pp104-105		 
	- p402
	- pp380-381

in this order.  It's ridiculous interrupts pending are subject to be
taken in "disabled -> mtc0 SR -> disabled" circumstance, and rather a
design mistake considering MIPS1 processor used to run sane and
straight atomic job with a single call of mtc0 SR.

With implementation to share common exception return path of
proc_trampoline with trap, intr and syscall, it'd be a single point of
occurence, and no other part is likely to have such an annoyance.

Tohru Nishimura