>>       - restore SR value on exception time with mtc0 insn.
>>       - because it has EXL bit, MIPS3 processor now blocks interrupts
>>         and enters critical section to restore the register values when
>>         exception was taken.
>
> If I remember correctly, there is a small window that EXL bit takes 
> effect since SR value is restored. So, if we simplely restore SR value
> (i.e. sets both interrupt mask bits and the EXL bit at the same time), 
> interrupt will be incorrectly enabled.

Hairly...  How about this?

	jal	_C_LABEL(xxx)
	nop

	lw	k1, sp, CALLFRAME_SIZ           # k1 points exception frame
        li      a0, MIPS3_SR_EXL
        mtc0    a0, MIPS_COP_0_STATUS           # EXL==1, disable interrupts
        nop                                     # 3 clock delay before
        lw      a0, FRAME_SR(k1)                # interrupts blocked
        nop                                     # R4000/4400
        mtc0    a0, MIPS_COP_0_STATUS           # restore SR exception

	<register restoration sequence>	

Tohru Nishimura