Nishimura-san wrote:
> I think exception returns can be done in following steps,
> 
> 	- restore SR value on exception time with mtc0 insn.
> 	- because it has EXL bit, MIPS3 processor now blocks interrupts
> 	  and enters critical section to restore the register values when
> 	  exception was taken.

If I remember correctly, there is a small window that EXL bit takes 
effect since SR value is restored. So, if we simplely restore SR value
(i.e. sets both interrupt mask bits and the EXL bit at the same time), 
interrupt will be incorrectly enabled.
--
soda