mhitch@netbsd.org ("Michael L. Hitch") writes:
> Set the boundary to NBPG for bus_dmamap_create().  The IOASIC DMA segment
> can not cross a page boundary.

"No, the IOASCI DMA segment cannot cross a 4K boundary."  The fact
that NBPG (our VM system page size on MIPS) and that boundary just
happens to be 4K is interesting, but not a great assumption.

In particular, if somebody tries to do a VPT-based page table approach
for MIPS, one thing I think they should consider is 64-bit PTEs and 8K
pages, i.e. treating both halves of each TLB entry as a single page.

That has the advantage that if you still want to keep the same flags
in the PTE (G, V, M, CCA:3, prot:2 -- eating 8 bits), you can still
accomodate mapping 8KB of VM with 64 bits on CPUs with a PA size of >
36 bits).

(8 bits of flags -> 24 bits of pfn to map 4k pages -> 36 bits of pa.)

Also, it has the advantage that if you want to add alpha-like
"granularity hint" support, so that the TLB mask registers can be used
to support wider mappings, with the existing PTE format you're already
out of space for that.


To make that more coherent, if we want to add support for systems with
> 36 bits of PA, or to support GH/wider-mask operationg in the TLBs,
we need to change the TLB format.

If we stick with 4k pages, we grow the PTEs by 2x either way.  If we
go to 8k pages we keep the PTEs the same size.


Not necessarily a good idea, but one that should be experimented
with... and that means making sure that hardware limitations are
encoded as such, and decoupled from the current software
implementation.  8-)



chris