At Sat, 16 Sep 2000 12:14:52 +0900 (JST),
nisimura@itc.aist-nara.ac.jp (Toru Nishimura) wrote:
> I guess the port uses 64bit TLB EntryLo0/1 to hardwire certain
> hardware register region populated beyond 32bit range to make it
> accessible.

TLB is still 32bit on _MIPS_PADDR_T_64BIT.
It changes just paddr_t size.

So, I think changing dmXc0 to mXc0 is no problem.

---
Shuichiro URATA
ur@a-r.org