Subject: 64 bit instructions
To: None <port-mips@netbsd.org>
From: Chuck Cranor <chuck@research.att.com>
List: port-mips
Date: 09/15/2000 20:17:13
actually, i am also sitting on the following diff that gets
rid of the 64 bit instructions that cause the IDT32364 to
choke. since we don't actually do 64 bit, they shouldn't
harm anything.
i could commit as is (as Toru Nishimura suggested to me in
an email), or i could abstract a bit ala REG_L/REG_S. is
anyone actively working on 64 bit mips3 support? if that
isn't currently a hot topic i'm inclined to follow Toru's
advice and commit as-is.
chuck
Index: locore_mips3.S
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/locore_mips3.S,v
retrieving revision 1.52
diff -c -r1.52 locore_mips3.S
*** locore_mips3.S 2000/09/13 06:48:04 1.52
--- locore_mips3.S 2000/09/16 00:12:45
***************
*** 435,441 ****
mtc0 a0, MIPS_COP_0_STATUS # restore the SR, disable intrs
mtlo t0
mthi t1
! dmtc0 k0, MIPS_COP_0_EXC_PC # set return address
REG_L AT, TF_BASE+TF_REG_AST(sp)
REG_L v0, TF_BASE+TF_REG_V0(sp)
REG_L v1, TF_BASE+TF_REG_V1(sp)
--- 435,441 ----
mtc0 a0, MIPS_COP_0_STATUS # restore the SR, disable intrs
mtlo t0
mthi t1
! mtc0 k0, MIPS_COP_0_EXC_PC # set return address
REG_L AT, TF_BASE+TF_REG_AST(sp)
REG_L v0, TF_BASE+TF_REG_V0(sp)
REG_L v1, TF_BASE+TF_REG_V1(sp)
***************
*** 513,524 ****
REG_S s1, FRAME_S1(k1)
REG_S s2, FRAME_S2(k1)
REG_S s3, FRAME_S3(k1)
! dmfc0 a2, MIPS_COP_0_BAD_VADDR # 3rd arg is fault address
REG_S s4, FRAME_S4(k1)
REG_S s5, FRAME_S5(k1)
REG_S s6, FRAME_S6(k1)
REG_S s7, FRAME_S7(k1)
! dmfc0 a3, MIPS_COP_0_EXC_PC # 4th arg is exception PC
REG_S t8, FRAME_T8(k1)
REG_S t9, FRAME_T9(k1)
REG_S gp, FRAME_GP(k1)
--- 513,524 ----
REG_S s1, FRAME_S1(k1)
REG_S s2, FRAME_S2(k1)
REG_S s3, FRAME_S3(k1)
! mfc0 a2, MIPS_COP_0_BAD_VADDR # 3rd arg is fault address
REG_S s4, FRAME_S4(k1)
REG_S s5, FRAME_S5(k1)
REG_S s6, FRAME_S6(k1)
REG_S s7, FRAME_S7(k1)
! mfc0 a3, MIPS_COP_0_EXC_PC # 4th arg is exception PC
REG_S t8, FRAME_T8(k1)
REG_S t9, FRAME_T9(k1)
REG_S gp, FRAME_GP(k1)
***************
*** 566,572 ****
# mtc0 a0, MIPS_COP_0_STATUS # still exception level
mtlo t0
mthi t1
! dmtc0 v0, MIPS_COP_0_EXC_PC # set return address
move k1, a1
REG_L AT, FRAME_AST(k1)
--- 566,572 ----
# mtc0 a0, MIPS_COP_0_STATUS # still exception level
mtlo t0
mthi t1
! mtc0 v0, MIPS_COP_0_EXC_PC # set return address
move k1, a1
REG_L AT, FRAME_AST(k1)
***************
*** 702,708 ****
# mtc0 a0, MIPS_COP_0_STATUS # this should disable interrupts
mtlo t0
mthi t1
! dmtc0 v0, MIPS_COP_0_EXC_PC # set return address
move k1, a1
REG_L AT, FRAME_AST(k1)
REG_L v0, FRAME_V0(k1)
--- 702,708 ----
# mtc0 a0, MIPS_COP_0_STATUS # this should disable interrupts
mtlo t0
mthi t1
! mtc0 v0, MIPS_COP_0_EXC_PC # set return address
move k1, a1
REG_L AT, FRAME_AST(k1)
REG_L v0, FRAME_V0(k1)
***************
*** 812,818 ****
mtc0 a0, MIPS_COP_0_STATUS # restore the SR, disable intrs
mtlo t0
mthi t1
! dmtc0 v0, MIPS_COP_0_EXC_PC # set return address
REG_L AT, TF_BASE+TF_REG_AST(sp)
REG_L v0, TF_BASE+TF_REG_V0(sp)
--- 812,818 ----
mtc0 a0, MIPS_COP_0_STATUS # restore the SR, disable intrs
mtlo t0
mthi t1
! mtc0 v0, MIPS_COP_0_EXC_PC # set return address
REG_L AT, TF_BASE+TF_REG_AST(sp)
REG_L v0, TF_BASE+TF_REG_V0(sp)
***************
*** 989,995 ****
REG_L v0, FRAME_EPC(a1)
mtlo t0
mthi t1
! dmtc0 v0, MIPS_COP_0_EXC_PC # set return address
nop # ??? how much delay ???
nop
--- 989,995 ----
REG_L v0, FRAME_EPC(a1)
mtlo t0
mthi t1
! mtc0 v0, MIPS_COP_0_EXC_PC # set return address
nop # ??? how much delay ???
nop
***************
*** 1058,1064 ****
*/
LEAF_NOPROFILE(mips3_TLBInvalidException)
.set noat
! dmfc0 k0, MIPS_COP_0_BAD_VADDR # get the fault address
li k1, VM_MIN_KERNEL_ADDRESS # compute index
bgez k0, _C_LABEL(mips3_KernGenException) # full trap processing
subu k0, k0, k1
--- 1058,1064 ----
*/
LEAF_NOPROFILE(mips3_TLBInvalidException)
.set noat
! mfc0 k0, MIPS_COP_0_BAD_VADDR # get the fault address
li k1, VM_MIN_KERNEL_ADDRESS # compute index
bgez k0, _C_LABEL(mips3_KernGenException) # full trap processing
subu k0, k0, k1
***************
*** 1081,1099 ****
bltz k0, outofworld # ASSERT(TLB entry exists)
lw k0, 0(k1) # get PTE entry
! dsll k0, k0, 34 # get rid of "wired" bit
! dsrl k0, k0, 34
! dmtc0 k0, MIPS_COP_0_TLB_LO0 # load PTE entry
and k0, k0, MIPS3_PG_V # check for valid entry
nop # required for QED5230
beq k0, zero, _C_LABEL(mips3_KernGenException) # PTE invalid
lw k0, 4(k1) # get odd PTE entry
! dsll k0, k0, 34
mfc0 k1, MIPS_COP_0_TLB_INDEX
! dsrl k0, k0, 34
sltiu k1, k1, MIPS3_TLB_WIRED_UPAGES # Luckily this is MIPS3_PG_G
or k1, k1, k0
! dmtc0 k0, MIPS_COP_0_TLB_LO1 # load PTE entry
nop
nop # required for QED5230
tlbwi # write TLB
--- 1081,1099 ----
bltz k0, outofworld # ASSERT(TLB entry exists)
lw k0, 0(k1) # get PTE entry
! sll k0, k0, 2 # get rid of "wired" bit
! srl k0, k0, 2
! mtc0 k0, MIPS_COP_0_TLB_LO0 # load PTE entry
and k0, k0, MIPS3_PG_V # check for valid entry
nop # required for QED5230
beq k0, zero, _C_LABEL(mips3_KernGenException) # PTE invalid
lw k0, 4(k1) # get odd PTE entry
! sll k0, k0, 2
mfc0 k1, MIPS_COP_0_TLB_INDEX
! srl k0, k0, 2
sltiu k1, k1, MIPS3_TLB_WIRED_UPAGES # Luckily this is MIPS3_PG_G
or k1, k1, k0
! mtc0 k0, MIPS_COP_0_TLB_LO1 # load PTE entry
nop
nop # required for QED5230
tlbwi # write TLB
***************
*** 1110,1128 ****
bltz k0, outofworld # assert(TLB Entry exists)
lw k0, 0(k1) # get PTE entry
! dsll k0, k0, 34 # get rid of wired bit
! dsrl k0, k0, 34
! dmtc0 k0, MIPS_COP_0_TLB_LO1 # save PTE entry
and k0, k0, MIPS3_PG_V # check for valid entry
nop # required for QED5230
beq k0, zero, _C_LABEL(mips3_KernGenException) # PTE invalid
lw k0, -4(k1) # get even PTE entry
! dsll k0, k0, 34
mfc0 k1, MIPS_COP_0_TLB_INDEX
! dsrl k0, k0, 34
sltiu k1, k1, MIPS3_TLB_WIRED_UPAGES # Luckily this is MIPS3_PG_G
or k1, k1, k0
! dmtc0 k0, MIPS_COP_0_TLB_LO0 # save PTE entry
nop
nop # required for QED5230
tlbwi # update TLB
--- 1110,1128 ----
bltz k0, outofworld # assert(TLB Entry exists)
lw k0, 0(k1) # get PTE entry
! sll k0, k0, 2 # get rid of wired bit
! srl k0, k0, 2
! mtc0 k0, MIPS_COP_0_TLB_LO1 # save PTE entry
and k0, k0, MIPS3_PG_V # check for valid entry
nop # required for QED5230
beq k0, zero, _C_LABEL(mips3_KernGenException) # PTE invalid
lw k0, -4(k1) # get even PTE entry
! sll k0, k0, 2
mfc0 k1, MIPS_COP_0_TLB_INDEX
! srl k0, k0, 2
sltiu k1, k1, MIPS3_TLB_WIRED_UPAGES # Luckily this is MIPS3_PG_G
or k1, k1, k0
! mtc0 k0, MIPS_COP_0_TLB_LO0 # save PTE entry
nop
nop # required for QED5230
tlbwi # update TLB
***************
*** 1152,1158 ****
*/
LEAF_NOPROFILE(mips3_TLBMissException)
.set noat
! dmfc0 k0, MIPS_COP_0_BAD_VADDR # get the fault address
li k1, VM_MIN_KERNEL_ADDRESS # compute index
subu k0, k0, k1
lw k1, _C_LABEL(Sysmapsize) # index within range?
--- 1152,1158 ----
*/
LEAF_NOPROFILE(mips3_TLBMissException)
.set noat
! mfc0 k0, MIPS_COP_0_BAD_VADDR # get the fault address
li k1, VM_MIN_KERNEL_ADDRESS # compute index
subu k0, k0, k1
lw k1, _C_LABEL(Sysmapsize) # index within range?
***************
*** 1173,1184 ****
addu k1, k1, k0
lw k0, 0(k1) # get PTE entry
lw k1, 4(k1) # get odd PTE entry
! dsll k0, k0, 34 # get rid of "wired" bit
! dsrl k0, k0, 34
! dmtc0 k0, MIPS_COP_0_TLB_LO0 # load PTE entry
! dsll k1, k1, 34
! dsrl k1, k1, 34
! dmtc0 k1, MIPS_COP_0_TLB_LO1 # load PTE entry
nop
nop # required for QED5230
tlbwr # write TLB
--- 1173,1184 ----
addu k1, k1, k0
lw k0, 0(k1) # get PTE entry
lw k1, 4(k1) # get odd PTE entry
! sll k0, k0, 2 # get rid of "wired" bit
! srl k0, k0, 2
! mtc0 k0, MIPS_COP_0_TLB_LO0 # load PTE entry
! sll k1, k1, 2
! srl k1, k1, 2
! mtc0 k1, MIPS_COP_0_TLB_LO1 # load PTE entry
nop
nop # required for QED5230
tlbwr # write TLB
***************
*** 1192,1201 ****
outofworld:
/* eret to panic so shutdown can use K2. Try to ensure valid $sp. */
la a0,_C_LABEL(panic)
! dmfc0 a2, MIPS_COP_0_EXC_PC
move a1, sp
sll k0, k0, PGSHIFT
! dmtc0 a0, MIPS_COP_0_EXC_PC # return to panic
li k1, VM_MIN_KERNEL_ADDRESS
addu a3, k0, k1
#if defined(DDB)
--- 1192,1201 ----
outofworld:
/* eret to panic so shutdown can use K2. Try to ensure valid $sp. */
la a0,_C_LABEL(panic)
! mfc0 a2, MIPS_COP_0_EXC_PC
move a1, sp
sll k0, k0, PGSHIFT
! mtc0 a0, MIPS_COP_0_EXC_PC # return to panic
li k1, VM_MIN_KERNEL_ADDRESS
addu a3, k0, k1
#if defined(DDB)
***************
*** 1237,1243 ****
*--------------------------------------------------------------------------
*/
LEAF(mips3_SetPID)
! dmtc0 a0, MIPS_COP_0_TLB_HI # Write the hi reg value
nop # required for QED5230
nop # required for QED5230
j ra
--- 1237,1243 ----
*--------------------------------------------------------------------------
*/
LEAF(mips3_SetPID)
! mtc0 a0, MIPS_COP_0_TLB_HI # Write the hi reg value
nop # required for QED5230
nop # required for QED5230
j ra
***************
*** 1314,1327 ****
and t1, a0, MIPS3_PG_ODDPG # t1 = Even/Odd flag
li v0, (MIPS3_PG_HVPN | MIPS3_PG_ASID)
and a0, a0, v0
! dmfc0 t0, MIPS_COP_0_TLB_HI # Save current PID
! dmtc0 a0, MIPS_COP_0_TLB_HI # Init high reg
and a2, a1, MIPS3_PG_G # Copy global bit
nop
nop
tlbp # Probe for the entry.
! dsll a1, a1, 34
! dsrl a1, a1, 34
bne t1, zero, 2f # Decide even odd
mfc0 v0, MIPS_COP_0_TLB_INDEX # See what we got
# EVEN
--- 1314,1327 ----
and t1, a0, MIPS3_PG_ODDPG # t1 = Even/Odd flag
li v0, (MIPS3_PG_HVPN | MIPS3_PG_ASID)
and a0, a0, v0
! mfc0 t0, MIPS_COP_0_TLB_HI # Save current PID
! mtc0 a0, MIPS_COP_0_TLB_HI # Init high reg
and a2, a1, MIPS3_PG_G # Copy global bit
nop
nop
tlbp # Probe for the entry.
! sll a1, a1, 2
! srl a1, a1, 2
bne t1, zero, 2f # Decide even odd
mfc0 v0, MIPS_COP_0_TLB_INDEX # See what we got
# EVEN
***************
*** 1334,1340 ****
nop
nop
nop
! dmtc0 a1, MIPS_COP_0_TLB_LO0 # init low reg0.
nop
nop # required for QED5230
tlbwi # update slot found
--- 1334,1340 ----
nop
nop
nop
! mtc0 a1, MIPS_COP_0_TLB_LO0 # init low reg0.
nop
nop # required for QED5230
tlbwi # update slot found
***************
*** 1349,1357 ****
#else
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # init mask.
#endif
! dmtc0 a0, MIPS_COP_0_TLB_HI # init high reg.
! dmtc0 a1, MIPS_COP_0_TLB_LO0 # init low reg0.
! dmtc0 a2, MIPS_COP_0_TLB_LO1 # init low reg1.
nop
nop # required for QED5230
tlbwr # enter into a random slot
--- 1349,1357 ----
#else
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # init mask.
#endif
! mtc0 a0, MIPS_COP_0_TLB_HI # init high reg.
! mtc0 a1, MIPS_COP_0_TLB_LO0 # init low reg0.
! mtc0 a2, MIPS_COP_0_TLB_LO1 # init low reg1.
nop
nop # required for QED5230
tlbwr # enter into a random slot
***************
*** 1370,1376 ****
nop
nop
nop
! dmtc0 a1, MIPS_COP_0_TLB_LO1 # init low reg1.
nop
nop # required for QED5230
tlbwi # update slot found
--- 1370,1376 ----
nop
nop
nop
! mtc0 a1, MIPS_COP_0_TLB_LO1 # init low reg1.
nop
nop # required for QED5230
tlbwi # update slot found
***************
*** 1385,1393 ****
#else
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # init mask.
#endif
! dmtc0 a0, MIPS_COP_0_TLB_HI # init high reg.
! dmtc0 a2, MIPS_COP_0_TLB_LO0 # init low reg0.
! dmtc0 a1, MIPS_COP_0_TLB_LO1 # init low reg1.
nop
nop # required for QED5230
tlbwr # enter into a random slot
--- 1385,1393 ----
#else
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # init mask.
#endif
! mtc0 a0, MIPS_COP_0_TLB_HI # init high reg.
! mtc0 a2, MIPS_COP_0_TLB_LO0 # init low reg0.
! mtc0 a1, MIPS_COP_0_TLB_LO1 # init low reg1.
nop
nop # required for QED5230
tlbwr # enter into a random slot
***************
*** 1397,1403 ****
nop # uses the tlb.
nop
nop
! dmtc0 t0, MIPS_COP_0_TLB_HI # restore PID
nop # required for QED5230
nop # required for QED5230
j ra
--- 1397,1403 ----
nop # uses the tlb.
nop
nop
! mtc0 t0, MIPS_COP_0_TLB_HI # restore PID
nop # required for QED5230
nop # required for QED5230
j ra
***************
*** 1428,1434 ****
nop
mfc0 t6, MIPS_COP_0_TLB_PG_MASK # save current pgMask
nop
! dmfc0 t0, MIPS_COP_0_TLB_HI # Get current PID
mtc0 a0, MIPS_COP_0_TLB_INDEX # Set the index register
nop
--- 1428,1434 ----
nop
mfc0 t6, MIPS_COP_0_TLB_PG_MASK # save current pgMask
nop
! mfc0 t0, MIPS_COP_0_TLB_HI # Get current PID
mtc0 a0, MIPS_COP_0_TLB_INDEX # Set the index register
nop
***************
*** 1438,1447 ****
nop
nop
mfc0 t2, MIPS_COP_0_TLB_PG_MASK # fetch the pgMask
! dmfc0 t3, MIPS_COP_0_TLB_HI # fetch the hi entry
! dmfc0 t4, MIPS_COP_0_TLB_LO0 # See what we got
! dmfc0 t5, MIPS_COP_0_TLB_LO1 # See what we got
! dmtc0 t0, MIPS_COP_0_TLB_HI # restore PID
mtc0 t6, MIPS_COP_0_TLB_PG_MASK # restore pgMask
nop
nop
--- 1438,1447 ----
nop
nop
mfc0 t2, MIPS_COP_0_TLB_PG_MASK # fetch the pgMask
! mfc0 t3, MIPS_COP_0_TLB_HI # fetch the hi entry
! mfc0 t4, MIPS_COP_0_TLB_LO0 # See what we got
! mfc0 t5, MIPS_COP_0_TLB_LO1 # See what we got
! mtc0 t0, MIPS_COP_0_TLB_HI # restore PID
mtc0 t6, MIPS_COP_0_TLB_PG_MASK # restore pgMask
nop
nop
***************
*** 2112,2118 ****
REG_L v0, FRAME_EPC(a1)
mtlo t0
mthi t1
! dmtc0 v0, MIPS_COP_0_EXC_PC
nop
move k1, a1
REG_L AT, FRAME_AST(k1)
--- 2112,2118 ----
REG_L v0, FRAME_EPC(a1)
mtlo t0
mthi t1
! mtc0 v0, MIPS_COP_0_EXC_PC
nop
move k1, a1
REG_L AT, FRAME_AST(k1)
***************
*** 2175,2181 ****
# p_addr starts on an odd page, need to set up 2 TLB entries
addu v0, v0, MIPS3_PG_ODDPG
! dmtc0 v0, MIPS_COP_0_TLB_HI # VPN = va
nop
nop
tlbp # probe VPN
--- 2175,2181 ----
# p_addr starts on an odd page, need to set up 2 TLB entries
addu v0, v0, MIPS3_PG_ODDPG
! mtc0 v0, MIPS_COP_0_TLB_HI # VPN = va
nop
nop
tlbp # probe VPN
***************
*** 2185,2206 ****
nop
bltz s0, entry1set
li s0, MIPS_KSEG0_START
! dmtc0 s0, MIPS_COP_0_TLB_HI
! dmtc0 zero, MIPS_COP_0_TLB_LO0
! dmtc0 zero, MIPS_COP_0_TLB_LO1
nop
nop
tlbwi
nop
nop
! dmtc0 v0, MIPS_COP_0_TLB_HI # set VPN again
entry1set:
li s0, 1
mtc0 s0, MIPS_COP_0_TLB_INDEX # TLB entry #1
or a2, MIPS3_PG_G
! dmtc0 a2, MIPS_COP_0_TLB_LO0 # lo0: upte[1] | PG_G
li a2, MIPS3_PG_G
! dmtc0 a2, MIPS_COP_0_TLB_LO1 # lo1: none | PG_G
nop
nop
tlbwi # set TLB entry #1
--- 2185,2206 ----
nop
bltz s0, entry1set
li s0, MIPS_KSEG0_START
! mtc0 s0, MIPS_COP_0_TLB_HI
! mtc0 zero, MIPS_COP_0_TLB_LO0
! mtc0 zero, MIPS_COP_0_TLB_LO1
nop
nop
tlbwi
nop
nop
! mtc0 v0, MIPS_COP_0_TLB_HI # set VPN again
entry1set:
li s0, 1
mtc0 s0, MIPS_COP_0_TLB_INDEX # TLB entry #1
or a2, MIPS3_PG_G
! mtc0 a2, MIPS_COP_0_TLB_LO0 # lo0: upte[1] | PG_G
li a2, MIPS3_PG_G
! mtc0 a2, MIPS_COP_0_TLB_LO1 # lo1: none | PG_G
nop
nop
tlbwi # set TLB entry #1
***************
*** 2211,2217 ****
addu v0, v0, -NBPG * 2 # backup to odd page mapping
entry0:
! dmtc0 v0, MIPS_COP_0_TLB_HI # VPN = va
nop
nop
tlbp # probe VPN
--- 2211,2217 ----
addu v0, v0, -NBPG * 2 # backup to odd page mapping
entry0:
! mtc0 v0, MIPS_COP_0_TLB_HI # VPN = va
nop
nop
tlbp # probe VPN
***************
*** 2221,2241 ****
nop
bltz s0, entry0set
li s0, MIPS_KSEG0_START
! dmtc0 s0, MIPS_COP_0_TLB_HI
! dmtc0 zero, MIPS_COP_0_TLB_LO0
! dmtc0 zero, MIPS_COP_0_TLB_LO1
nop
nop
tlbwi
nop
nop
! dmtc0 v0, MIPS_COP_0_TLB_HI # set VPN again
entry0set:
mtc0 zero, MIPS_COP_0_TLB_INDEX # TLB entry #0
or a1, MIPS3_PG_G
! dmtc0 a1, MIPS_COP_0_TLB_LO0 # upte[0] | PG_G
or a2, MIPS3_PG_G
! dmtc0 a2, MIPS_COP_0_TLB_LO1 # upte[1] | PG_G
nop
nop
tlbwi # set TLB entry #0
--- 2221,2241 ----
nop
bltz s0, entry0set
li s0, MIPS_KSEG0_START
! mtc0 s0, MIPS_COP_0_TLB_HI
! mtc0 zero, MIPS_COP_0_TLB_LO0
! mtc0 zero, MIPS_COP_0_TLB_LO1
nop
nop
tlbwi
nop
nop
! mtc0 v0, MIPS_COP_0_TLB_HI # set VPN again
entry0set:
mtc0 zero, MIPS_COP_0_TLB_INDEX # TLB entry #0
or a1, MIPS3_PG_G
! mtc0 a1, MIPS_COP_0_TLB_LO0 # upte[0] | PG_G
or a2, MIPS3_PG_G
! mtc0 a2, MIPS_COP_0_TLB_LO1 # upte[1] | PG_G
nop
nop
tlbwi # set TLB entry #0
***************
*** 2257,2266 ****
mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
li v0, (MIPS3_PG_HVPN | MIPS3_PG_ASID)
! dmfc0 t0, MIPS_COP_0_TLB_HI # save current ASID
mfc0 t3, MIPS_COP_0_TLB_PG_MASK # save current pgMask
and a0, a0, v0 # make sure valid entryHi
! dmtc0 a0, MIPS_COP_0_TLB_HI # look for the vaddr & ASID
nop
nop
tlbp # probe the entry in question
--- 2257,2266 ----
mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
li v0, (MIPS3_PG_HVPN | MIPS3_PG_ASID)
! mfc0 t0, MIPS_COP_0_TLB_HI # save current ASID
mfc0 t3, MIPS_COP_0_TLB_PG_MASK # save current pgMask
and a0, a0, v0 # make sure valid entryHi
! mtc0 a0, MIPS_COP_0_TLB_HI # look for the vaddr & ASID
nop
nop
tlbp # probe the entry in question
***************
*** 2271,2279 ****
#nop # -slip-
bltz v0, 1f # index < 0 then skip
li t1, MIPS_KSEG0_START # invalid address
! dmtc0 t1, MIPS_COP_0_TLB_HI # make entryHi invalid
! dmtc0 zero, MIPS_COP_0_TLB_LO0 # zero out entryLo0
! dmtc0 zero, MIPS_COP_0_TLB_LO1 # zero out entryLo1
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # zero out pageMask
nop
nop
--- 2271,2279 ----
#nop # -slip-
bltz v0, 1f # index < 0 then skip
li t1, MIPS_KSEG0_START # invalid address
! mtc0 t1, MIPS_COP_0_TLB_HI # make entryHi invalid
! mtc0 zero, MIPS_COP_0_TLB_LO0 # zero out entryLo0
! mtc0 zero, MIPS_COP_0_TLB_LO1 # zero out entryLo1
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # zero out pageMask
nop
nop
***************
*** 2281,2287 ****
nop
nop
1:
! dmtc0 t0, MIPS_COP_0_TLB_HI # restore current ASID
mtc0 t3, MIPS_COP_0_TLB_PG_MASK # restore pgMask
nop
nop
--- 2281,2287 ----
nop
nop
1:
! mtc0 t0, MIPS_COP_0_TLB_HI # restore current ASID
mtc0 t3, MIPS_COP_0_TLB_PG_MASK # restore pgMask
nop
nop
***************
*** 2310,2325 ****
nop
nop
tlbr # obtain an entry
! dmfc0 a0, MIPS_COP_0_TLB_LO1
#nop # -slip-
#nop # -slip-
and a0, a0, MIPS3_PG_G # check to see it has G bit
bnez a0, 2f
nop
! dmtc0 v0, MIPS_COP_0_TLB_HI # make entryHi invalid
! dmtc0 zero, MIPS_COP_0_TLB_LO0 # zero out entryLo0
! dmtc0 zero, MIPS_COP_0_TLB_LO1 # zero out entryLo1
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # zero out mask entry
nop
nop
--- 2310,2325 ----
nop
nop
tlbr # obtain an entry
! mfc0 a0, MIPS_COP_0_TLB_LO1
#nop # -slip-
#nop # -slip-
and a0, a0, MIPS3_PG_G # check to see it has G bit
bnez a0, 2f
nop
! mtc0 v0, MIPS_COP_0_TLB_HI # make entryHi invalid
! mtc0 zero, MIPS_COP_0_TLB_LO0 # zero out entryLo0
! mtc0 zero, MIPS_COP_0_TLB_LO1 # zero out entryLo1
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # zero out mask entry
nop
nop
***************
*** 2348,2360 ****
mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
li v0, MIPS_KSEG0_START # invalid address
! dmfc0 t0, MIPS_COP_0_TLB_HI # save current ASID
mfc0 t1, MIPS_COP_0_TLB_WIRED
mfc0 t2, MIPS_COP_0_TLB_PG_MASK # save current pgMask
! dmtc0 v0, MIPS_COP_0_TLB_HI # make entryHi invalid
! dmtc0 zero, MIPS_COP_0_TLB_LO0 # zero out entryLo0
! dmtc0 zero, MIPS_COP_0_TLB_LO1 # zero out entryLo1
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # zero out pageMask
# do {} while (t1 < a0)
--- 2348,2360 ----
mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
li v0, MIPS_KSEG0_START # invalid address
! mfc0 t0, MIPS_COP_0_TLB_HI # save current ASID
mfc0 t1, MIPS_COP_0_TLB_WIRED
mfc0 t2, MIPS_COP_0_TLB_PG_MASK # save current pgMask
! mtc0 v0, MIPS_COP_0_TLB_HI # make entryHi invalid
! mtc0 zero, MIPS_COP_0_TLB_LO0 # zero out entryLo0
! mtc0 zero, MIPS_COP_0_TLB_LO1 # zero out entryLo1
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # zero out pageMask
# do {} while (t1 < a0)
***************
*** 2369,2375 ****
bne t1, a0, 1b
nop
! dmtc0 t0, MIPS_COP_0_TLB_HI # restore ASID
mtc0 t2, MIPS_COP_0_TLB_PG_MASK # restore pgMask
nop
nop
--- 2369,2375 ----
bne t1, a0, 1b
nop
! mtc0 t0, MIPS_COP_0_TLB_HI # restore ASID
mtc0 t2, MIPS_COP_0_TLB_PG_MASK # restore pgMask
nop
nop