hi-

    i just committed the following change to handle different base
sizes on the RC32364:

    IDT32364's Config register uses a different base for IC/DC (instruction
    and data cache sizes).   R4000 uses 2^(12+IC) and 2^(12+DC).  IDT32364
    uses 2^(9+IC) and 2^(9+DC).

    abstract around the problem by making the base a parameter to the
    MIPS3_CONFIG_CACHE_SIZE macro.   we pass the base down from mips_vector_init
    to mips3_vector_init and to mips3_ConfigCache (where it is used).
    
    XXX: someone with an MIPS3_4100 should switch to this and get rid
    of the ugly ifdefs in cpuregs.h


i'm going to be working on the cache routines shortly, as instructed
below.

chuck


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NetBSD 1.5E (IDT) #53: Fri Sep 15 19:55:41 EDT 2000
    chuck@xbsd.research.att.com:/usr/users/chuck/work/idt/idtmips/sys/arch/idtmips/compile/IDT
total memory = 31744 KB
avail memory = 27360 KB
using 422 buffers containing 1688 KB of memory
mainbus0 (root)
cpu0 at mainbus0: IDT RC32364 CPU (0x2620) Rev. 2.0 with software emulated floating point Rev. 0.0
cpu0: L1 cache: 8KB/16B instruction, 2KB/16B data, two way set associative
cpu0: No L2 cache
L1 cache: two way, but Inst/Data line size = 16/16
Please fix implementation of mips3_*Flush*Cache
halted.