Chuck Cranor wrote:
> 
> hi-
> 
>     one of the groups here is looking at supporting the IDT MIPS_RC32364
> core. (c.f. http://www.idt.com/products/pages/Processors-79RC32364.html)
> the 32364 has a R4000'ish MMU, except that it doesn't support 64 bit
> instructions.   specifically, the differences are:

I would prefer to handle this with minor #ifdeffing, perferably with
macros to hide the cpu dependancy where possible so that reading the
code looks clean.  Similar to the way REG_L was done for the 64b
ctx case.  This could handle dmtc0/mtc0 and the context register.

The tlb code probably needs short sequences that are #ifed.

Self modifying code seems extreme.  Anyone with this CPU would likely
not need to run the same kernel on another machine.

> also, in the current locore_mips3.S, is it necessary to use
> 64 bit instrucions on 32 bit cp0 registers?  (e.g. in the
> mips3_TLBMiss vector "dmtc0" is used to write to MIPS_COP_0_TLB_LO1
> which is a 32 bit register as far as i know ... why not use
> "mtc0" instead?).

I'm not 100% sure, and have wondered the same thing.  Lots of
implementations really don't care.  Systems that support more
physical bits (R10K, maybe even R4K) probably have bigger page
entries.   The QED processor I'm using now is 32b.

jeffs