> > I have been toying the idea that master interrupt MIPS_SR_INT_IE is
> > kept on when cpu_intr() is called while HARD_INT bits in SR turned
> > off.  Then, cpu_intr() can enable HART_INT bits (the effect like
> > spllower) gradually, say, as you wish, to reflect interrupt priorities
> > of devices.
> 
> The platform code can do this itself.  Our (internal) platform lowers
> the spl to the appropriate spl before calling the isr.  Handling
> SR_INT_IE is easy enough, but it would be a cleaner interface.

This discussion reminds me a related issue.

Why do syscall() entry and trap() entry of mips/mips/trap.c disable
software interrupts at the first of the function?
As far as I know, other platform don't do this.

I suppose that disabling software interrupts at syscall() and trap()
might makes performace worse...
--
soda