>> Could it be possible for NetBSD to use the Mips 's CPU timer
>> to call hardclock ?
>
> Yes, that's no problem.

A side note about how cpu_intr() is organized.

cpu_intr() is called with master interrupt MIPS_SR_INT_IE off.  This
is (was) an artifact of R3000 'stacked interrupt mask', and
locore_mips3.S simulates locore_mips1.S behaviour.  NetBSD/cobalt
seems to handle all of HARD_INT requests leaving MIPS_SR_INT_IE off.
I guess that's the reason why NetBSD/cobalt 'slips' clock severely
when system load is high.

I have been toying the idea that master interrupt MIPS_SR_INT_IE is
kept on when cpu_intr() is called while HARD_INT bits in SR turned
off.  Then, cpu_intr() can enable HART_INT bits (the effect like
spllower) gradually, say, as you wish, to reflect interrupt priorities
of devices.

This scheme can be implemented easily in R4000 and its descenders
because they have an exception level control MIPS3_SR_EXL bit
independent of MIPS_SR_INT_IE.  MIPS3_SR_EXL works a handy 'guard' to
protect critical sections.  In the most of cases MIPS_SR_INT_IE can be
left untouched.

On the other hand, since R3000 automatically makes push+pop the 3
level interrupt (and K/U indication) stack upon exception enter and
exit, it's (somehow) complicated to re-enable MIPS_SR_INT_IE bit in
critical sections.

Tohru Nishimura
Nara Institute of Science and Technology