Subject: Re: more on understanding caches.
To: None <nisimura@itc.aist-nara.ac.jp, port-m88k@netbsd.org, port-mips@netbsd.org>
From: Noriyuki Soda <soda@sra.co.jp>
List: port-mips
Date: 08/09/2000 19:38:34
> Here goes some scenario to run cache primitives;
	:
> - DMA read/write
> 	If DMA is a pullup from device, the target memory range must get
> 	invalidated with "Invalidate Dcache" for DMA.  If DMA is a
> 	push down to device, the cache contents must be written to target
> 	range with "Synchronize(+Invalidate) Dcache" for DMA.
> 
> void	
> _bus_dmamap_sync(t, map, off, len, ops)
> {
>     ... IF write-back cache ...
> 	if (ops & BUS_DMASYNC_PREWRITE)
> 		Synchronize+Invalidate Dcache
> 	else if (ops & BUS_DMASYNC_POSTREAD)
> 		Invalidate Dcache

Invalidation is not needed for BUS_DMASYNC_PREWRITE.

>     ... IF write-thru cache ...
> 	if (ops & BUS_DMASYNC_POSTREAD)
> 		Invalidate Dcache

Since invalidation is not needed for BUS_DMASYNC_PREWRITE, we don't
have to distinguish write-back cache and write-through cache here.
--
soda