Jeff Smith wrote:
> Can you try this Wayne?

Here is the patch I had in mind.

jeffs

*** locore_mips3.S	2000/07/25 18:06:49	1.43
--- locore_mips3.S	2000/07/27 23:06:36
***************
*** 1564,1570 ****
   *		vaddr_t addr; vsize_t len;
   *
   *	Flush instruction cache for range of addr to addr + len - 1.
!  *	The address can be any valid address so long as no TLB misses
occur.
   *	Assumes a cache line size of 16 bytes for speed.
   *
   * Results:
--- 1564,1570 ----
   *		vaddr_t addr; vsize_t len;
   *
   *	Flush instruction cache for range of addr to addr + len - 1.
!  *	The address is reduced to a kseg0 index.
   *	Assumes a cache line size of 16 bytes for speed.
   *
   * Results:
***************
*** 1577,1583 ****
--- 1577,1588 ----
  
*----------------------------------------------------------------------------  
*/
  LEAF(mips3_FlushICache)
+ 	lw	a2, mips_L1ICacheSize
+ 	addu	a2, -1
+ 	and	a0, a0, a2	# get index into primary cache
  	addu	a1, 127		# Align
+ 	li	a2, MIPS_KSEG0_START
+ 	addu	a0, a0, a2
  	srl	a1, a1, 7	# Number of unrolled loops
  1:
  	cache	C_IINV_I, 0(a0)