Wayne Knowles wrote:

> It is interesting to note that the machine that won't boot is R4k based:

oops.


> It may be more than just a write-back cache issue.  The external L2
> cache is
> unified in which case you have to be careful about what order you touch
> the
> I and D caches.    How does the L2 cache differ from the QED 5231
> system?

The QED box we use has only primary caches, and uses different flush
ops to handle the 2way caches.  I would think the checked in code
would work on the R4400SC.

Looking back at the e-mail logs, the kernel is missing on a K2
address, probably during the I cache flush.  The D cache flush
converts to a K0 address with the proper index like the _2way
code does.

I think the correct fix is to make mips3_FlushICache() convert
a0 into a K0 address with the proper cache index like
mips3_FlushDCache().  This should avoid any TLB misses in this
path.

Can you try this Wayne?

Thanks

jeffs