Subject: Re: more on understanding caches.
To: Michael L. Hitch <email@example.com>
From: Chris G. Demetriou <firstname.lastname@example.org>
Date: 06/29/2000 13:38:20
> Because the mips1 cache is write-through, so when an instruction is
> modified (setting/clearing breakpoints), the data is written to memory.
> The I cache is flushed to make sure the modified data is executed, not
> the data in cache.
*sigh* so many variations, so little actual documentation in the
actually, searching for 'through' shows (among other things):
* TX3922 write-through D-cache mode.
* for TX3912, no meaning. (no write-back mode)
but that's nowhere near the actual r3900 cache op code.
> I'm confused :-) Is the r3900 considered mips1? And does it have
> write-back cache? If so, then it's likely there are lots of places
> that don't handle the cache correctly.
yes, it's considered "mips1" by the code, at least in many places. it
looks like its caches are always used in write-through mode. (some
members of the family are only write-through, some appear to support
both modes but can be set one way or another, and are set to
good call (by you and Jeff).