On 29 Jun 2000, Chris G. Demetriou wrote:

> The (more) generic questions:
> 
> 	* why does pmap_procwr() flush both I and D for mips3, but
> 	  only flush I for mips1?

  Because the mips1 cache is write-through, so when an instruction is
modified (setting/clearing breakpoints), the data is written to memory.
The I cache is flushed to make sure the modified data is executed, not
the data in cache.

  The mip3 has to flush the D cache to ensure the data gets written to
memory so that the correct data gets into the I cache to be executed.

> 	* most FlushDCache routines seem to use writeback-invalidate.
> 	  the r3900 one seems to use invalidate (i.e., no
> 	  write-back!).  (The FlushCache routine seems to accomplish
> 	  the writeback-invalidate by loading data.)
> 
> 	  Given the use of FlushDCache for mips1 in pmap_remove_pv,
> 	  this would seem to be incorrect...

  I'm confused :-)  Is the r3900 considered mips1?  And does it have
write-back cache?  If so, then it's likely there are lots of places
that don't handle the cache correctly.  When I was mucking around in
pmap.c and other places, the only mips1 system supported was the
DECstations (which I'd guess all the code was designed for at the start),
and the cache was only physically-indexed and write-through.

--
Michael L. Hitch			mhitch@montana.edu
Computer Consultant
Information Technology Center
Montana State University	Bozeman, MT	USA