In message <5thfapqyy8.fsf@highland.sibyte.com> Chris G. Demetriou writes:
: Anyway, the way I'd do this is define ops which flush the l1 and l2
: caches in the 'standard' ways, for the standard line sizes.
: CPU-specific code would fill in the l1 info, and the l2 info if
: appropriate (is that ever appropriate on MIPS?), and board-specific
: code would fill in the l2 (and further) otherwise.

The R4400MP chips have direct support for L2 cache.  The R4400PC that
I have in my Deskstation rPC44 doesn't have a snooping L2 cache.  Its
L2 cache is purely a PCAT memory system cache, which isn't under
control of the CPU.  I don't know what any other chips in the MIPS
family do for this.

Warner