"Chris G. Demetriou" wrote:

> > What does SiByte have?  EEtimes didn't say :-)
> 
> I could tell you, but I'd have to kill you.  I'm sure you know how it
> goes.  8-)

32KB 4 way I and D caches.  You can repeat what's
in the press releases :-)

You should be fairly motivated then to help make multi
way cache support more efficient than it is now.  The
sibyte processor would take it pretty hard the way it
is now unless the cache ops are more efficent than other
implementations.

jeffs