Chris:

Each of your e-mails has a ton of things in it.

For the first part, there are a lot of cache op
varieties for the various platforms.  I don't think
the current set-up is that bad.

We should make it easy for the various mips platforms
to include their cacheop flavor w/o indirection if they
only need one set of ops.  For platforms that like pmax
that support multiple processors with one kernel, they
can pay the jr overhead.   I don't think that's too hard.

I think the MIPS3_L2CACHE_ABSET code needs work for
when it means "fix virtual coherency problems".  Our
QED 5200 platform does a lot of cacheflushing and it
feels like we have too many.

Along the lines of cache flushing policy, that needs
work with the VCE avoidance, and if hit or index ops
give the best performance for a variety of machines.

It really would be good for this to get better.  Likewise
I've wanted to look at some of the policy code, but havn't
had time to get far on it.

jeffs