>>Newer designs of R3000 (A?) have write buffer circuit built inside
>>eliminating an external logics.  Now my question is; how such the
>>builtin WB can be drained?  I heard that WB drain can be done lw
>>operation of a 32bit quantity in KSEG1 space.
>
>Yep. That's how the r3000 pmaxes force a writebuffer drain.  You
>should not have to read the ioasic register; the writebuffer hardware
>does a "memory write barrier" and drains pending writes before an
>uncached read 

On DECstation reading IOASIC register happens to be possibly faster
than to read 0xa000.0000 whose body might be implemented by ROM or
flash.  I guess that's the See How MIPS runs would put a special remark.

Tohru Nishimura