On  Mar 27, 2000 13:12:18, Toru Nishimura
<nisimura@itc.aist-nara.ac.jp> writes:



>I have a question about MIPS processor writebuffer operation.
>
>I heard that early implementation of R2000/R3000 processors had no
>write buffer circuit inside to isolate CPU from memory subsystem.
>There were companion chips for R2000/R3000 to implement write buffer.
>Smart engineers could design their own memory control logic as a part
>of 'system controller chip' for particular computer products.   This
>is what Digital did for some of DS5000.

There may have been a standard mipsco writebuffer part for the
r2000/r2000A, but no enforced standard for interfacing the dratted
thing.  So (as with the r2010 FPU interrupt signal) different vendors
hooked the 'writebuffer is done' up to vrious CPU condition-code pins
for "coprocessor X is usable).


IIRC, the "standard" recommended by MIPSco was to use the CU0 bit.
However, the writebuffer on the DECsystem 5100s and 5400s was wired
differently, and code uses "bc3f" to loop waiting for a writebuffer
drain.  (On one or other of them you had to write to some special
address to start the write drain, too).

>Newer designs of R3000 (A?) have write buffer circuit built inside
>eliminating an external logics.  Now my question is; how such the
>builtin WB can be drained?  I heard that WB drain can be done lw
>operation of a 32bit quantity in KSEG1 space.

Yep. That's how the r3000 pmaxes force a writebuffer drain.  You
should not have to read the ioasic register; the writebuffer hardware
does a "memory write barrier" and drains pending writes before an
uncached read (which are marginally faster from memory than the IOCTL
asic).  Whether the writebuffer is integrated or an external r3220, I
honestly dont recall.

I beleive the ULTRIX code for the 5500 (aka kn220, which had an r3000
core) allocated an otherwise-unused variable in locore bss, and
trigger a flush by reading from the uncached address of that variable.