How many nop's are required given most 'hazardous' CP0 MIPS processors
to make the following work correctly?

Tohru Nishimura

LEAF(mips3_TBIAP)
        mfc0    v1, MIPS_COP_0_STATUS           # save status register
        mtc0    zero, MIPS_COP_0_STATUS         # disable interrupts

        mfc0    t1, MIPS_COP_0_TLB_WIRED
        move    t2, a0
        li      v0, MIPS_KSEG0_START            # invalid address

        # do {} while (t1 < t2)
1:      
        mtc0    t1, MIPS_COP_0_TLB_INDEX        # set index
        nop
        nop
        tlbr                                    # obtain an entry
        dmfc0   a0, MIPS_COP_0_TLB_LO1
        nop
        nop
        andi    a0, a0, MIPS3_PG_G              # check to see it has G bit
        bnez    a0, 2f
        nop     

        dmtc0   v0, MIPS_COP_0_TLB_HI           # make entryHi invalid
        dmtc0   zero, MIPS_COP_0_TLB_LO0        # zero out entryLo0
        dmtc0   zero, MIPS_COP_0_TLB_LO1        # zero out entryLo1
        mtc0    zero, MIPS_COP_0_TLB_PG_MASK    # zero out mask entry
        nop
        nop
        tlbwi                                   # invalidate the TLB entry
        nop
        #nop
2:
        addu    t1, t1, 1
        bne     t1, t2, 1b
        nop

        j       ra                              # new ASID will be set soon
        mtc0    v1, MIPS_COP_0_STATUS           # restore status register
	END(mips3_TBIAP)
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