> I'll post mips3_cpu_switch_resume() later.

Here comes it.   If we can assume USPACE is aligned at 8KB boundary of
KSEG2, code would be like;

--
/*
 * void mips3_cpu_switch(struct proc *newproc)
 *
 * Wiredown the USPACE of newproc with TLB entry#0.  Check
 * whether target USPACE is already refered by some TLB entry(s)
 * before that, and make sure TBIS(them) in the case.
 */
LEAF_NOPROFILE(mips3_cpu_switch_resume)
	lw	a1, P_MD_UPTE_0(a0)		# a1 = upte[0]
	lw	a2, P_MD_UPTE_1(a0)		# a2 = upte[1]
	lw	s0, P_ADDR(a0)			# va = p->p_addr
	li	s2, MIPS_KSEG2_START
	blt	s0, s2, resume
	nop

	dmtc0	s0, MIPS_COP_0_TLB_HI		# VPN = va
	nop
	nop
	tlbp					# probe VPN
	nop
	nop
	mfc0	s1, MIPS_COP_0_TLB_INDEX
	nop
	bltz	s1, entry0set
	li	s0, MIPS_KSEG0_START
	dmtc0	s0, MIPS_COP_0_TLB_HI
	dmtc0	zero, MIPS_COP_0_TLB_LO0
	dmtc0	zero, MIPS_COP_0_TLB_LO1
	nop
	nop
	tlbwi
	nop
	nop
	dmtc0	s0, MIPS_COP_0_TLB_HI		# set VPN again
entry0set:
	mtc0	zero, MIPS_COP_0_TLB_INDEX	# TLB entry #0
	ori	a1, MIPS3_PG_G
	dmtc0	a1, MIPS_COP_0_TLB_LO0		# upte[0] | PG_G
	ori	a2, MIPS3_PG_G
	dmtc0	a2, MIPS_COP_0_TLB_LO1		# upte[1] | PG_G
	nop
	nop
	tlbwi					# set TLB entry #0
	nop
	nop

resume:
	j	ra
	nop
	END(mips3_cpu_switch_resume)

--
Tohru Nishimura