Subject: Hardwiring device registers
To: None <port-mips@netbsd.org>
From: Toru Nishimura <nisimura@itc.aist-nara.ac.jp>
List: port-mips
Date: 04/03/2000 12:56:22
Here is a hack made at last Sunday afternoon, to absorb the target
specific device mapping in nicer way. 

Tohru Nishimura
--

struct hardwired {
	int	tlbindex;
	int	pgsize;
	vaddr_t	va;
	paddr_t	pa0, pa1;
};

struct hardwired picawired[] = {
	{ 2,
	MIPS3_PG_SIZE_256K,
	R4030_V_LOCAL_IO_BASE,
	R4030_P_LOCAL_IO_BASE, PICA_P_INT_SOURCE, },
	{ 3,
	MIPS3_PG_SIZE_1M,
	R4030_V_LOCAL_VIDEO_CNTRL,
	R4030_P_LOCAL_VIDEO_BASE,
	R4030_P_LOCAL_VIDEO_BASE + PICA_S_LOCAL_VIDEO_CTRL/2, },
	{ 4, 
	MIPS3_PG_SIZE_1M,
	PICA_V_EXTND_VIDEO_CTRL,
	PICA_P_EXTND_VIDEO_CTRL,
	PICA_P_EXTND_VIDEO_CTRL + PICA_S_EXTND_VIDEO_CTRL/2, },
	{ 5,
	MIPS3_PG_SIZE_4M,
	PICA_V_LOCAL_VIDEO,
	PICA_P_LOCAL_VIDEO,
	PICA_P_LOCAL_VIDEO + PICA_S_LOCAL_VIDEO/2, },
	{ 6,
	MIPS3_PG_SIZE_16M,
	PICA_V_ISA_IO,
	PICA_P_ISA_IO, PICA_P_ISA_MEM, },
};
int npicawired = sizeof(picawired) / sizeof(struct hardwired);

struct hardwired tynewired[] = {
	{ 2,
	MIPS3_PG_SIZE_256K,
	TYNE_V_BOUNCE,
	TYNE_P_BOUNCE, 0 },
	{ 3,
	MIPS3_PG_SIZE_1M,
	TYNE_V_ISA_IO,
	TYNE_P_ISA_IO, 0, },
	{ 4,
	MIPS3_PG_SIZE_1M,
	TYNE_V_ISA_MEM,
	TYNE_P_ISA_MEM, 0, },
	{ 5,
	MIPS3_PG_SIZE_4K,
	0xe3000000,
	0x03ffc000, 0, },
};
int ntynewired = sizeof(tynewired) / sizeof(struct hardwired);

void
tlb_init_pica()
{
	struct hardwared *p;
	struct tlb tlb;

	p = picawired;
	for (i = 0; i < npicawired; i++) {
		tlb.tlb_mask = p->pgsize;
		tlb.tlb_hi = misp3_vad_to_vpn(p->va);
		tlb.tlb_lo0 = vad_to_fn(p->pa0) | MIPS3_PG_N | MIPS3_PG_G;
		tlb.tlb_lo1 = vad_to_fn(p->pa1) | MIPS3_PG_N | MIPS3_PG_G;
		mips3_TLBWriteIndexVPS(p->tlbindex, &tlb);
		p += 1;
	}
	/* SETWIRED(7) */
}

void
tlb_init_tyne()
{
	struct hardwared *p;
	struct tlb tlb;

	p = tynewired;
	for (i = 0; i < ntynewired; i++) {
		tlb.tlb_mask = p->pgsize;
		tlb.tlb_hi = misp3_vad_to_vpn(p->va);
		tlb.tlb_lo0 = vad_to_fn(p->pa0) | MIPS3_PG_N | MIPS3_PG_G;
		tlb.tlb_lo1 = vad_to_fn(p->pa1) | MIPS3_PG_N | MIPS3_PG_G;
		mips3_TLBWriteIndexVPS(p->tlbindex, &tlb);
		p += 1;
	}
	/* SETWIRED(6) */
}
--