Subject: Re: flushing write buffer
To: None <simonb@NetBSD.ORG>
From: Toru Nishimura <firstname.lastname@example.org>
Date: 03/28/2000 17:10:52
The intent of my Q was to replace mips1_wbflush() routine found in
locore_mips1.S with one which do 'standard thing' in general cases.
> you can ensure
> that the write buffer is empty by performing an uncached load
> from anywhere (which will stall the CPU until the writes have
> finished and the load has finished too). This is inefficient;
> you can minimize the overhead by loading from the fastest memory
> available to you.
So, isn't it ok to provide generic but possibly less-optimal default;
lui v0, 0x8000
lw v0, 0(v0)
For R3000A-or-later model only ports, it'd be nice to have #define for
__asm __volatile making sure KSEG1 load.
> For those who never want to think about it again, a write
> to memory followed by an uncached read from the same address
> (with a `sync' in between the two if you're running on a MIPS
> III or later CPU) will flush out the write FIFO on any MIPS CPU
> built to date
Does it mean there is a handy improvement of bus_space_write_N()?