At Mon, 6 Mar 2000 00:28:24 +0900 (JST),
Noriyuki Soda <soda@sra.co.jp> wrote:
> BTW, page 61 of Dominic Sweetman's "See MIPS Run" ("3.4.2 Config
> Register: R4x00 Configuration") says:
> 	SC	In R4000 and R5000 CPUs and their immediate
> 		descendants, this field is writable and acts as a
> 		sofware-controlled enable for the secoundary cache;
> Does anyone know the raitionale of this?
> Is this description just wrong?

SC field is read only on both R4000 and R5000.
Although R5000 has secondary cache enable on bit12 and software can
modify this field.

---
Shuichiro URATA
ur@a-r.org