Subject: Re: k0/k1 register while mulhi/mullo manipulation
To: None <,>
From: Toru Nishimura <>
List: port-mips
Date: 02/24/2000 18:34:47
>> if the new code sequence got an interrupt after 'lw k0, ...'
>> before 'mtc0 a0, ...', k0 would be trashed by the interrupt handler
>> (not by mtlo/mthi insns) and glok in a hidious way.  How is this
>> senario?
> Oh yeah, that's a bug all right. I've worked on (and fixed) debug stubs
> that made this sort of mistake.

Thank you all who responded to me.  I cound not figure out without
helps the cause of why k0 value seems trashed.

Tohru Nishimura