Subject: Re: k0/k1 register while mulhi/mullo manipulation
To: None <>
From: Toru Nishimura <>
List: port-mips
Date: 02/24/2000 14:32:10
> The TLB miss handler *shouldn't* be a consideration in the exception
> handler return - it is only accessing the kernel stack stack at that
> point, and the kernel stack pages should be in the wired TLB entries.
> [I'm not real sure if they are currently in the wired entries.  It's been
> a while since I've been in that part of the code.]

NetBSD/mips R3000/R4000 codes run USPACEs using wired TLB entries, but
they have their own unique KSEG2 addresses, i.e., NetBSD has no UADDR
any more, _the_ very archaic feature of UNIX.  (I'm still wondering why
KSEG0 range is not used)

Tohru Nishimura