Subject: Re: k0/k1 register while mulhi/mullo manipulation
To: None <,>
From: Michael L. Hitch <>
List: port-mips
Date: 02/23/2000 12:34:02
On Wed, 23 Feb 2000, Warner Losh wrote:

> In message <> Jason Thorpe writes:
> : Right, well, in our case, k0 and k1 are used in the TLB miss handlers.
> Aren't the TLB miss hanlders called with interrupts off?  They are
> interrupt hanlders...  Or is that your point:  They are used there and
> only there.

  The point would be that you can't use the k0/k1 registers in the kernel
where you might get a TLB miss (i.e. accessing KSEG2 or USR space without
ensuring that address space is currently loaded in the TLB).

  The TLB miss handler *shouldn't* be a consideration in the exception
handler return - it is only accessing the kernel stack stack at that
point, and the kernel stack pages should be in the wired TLB entries.
[I'm not real sure if they are currently in the wired entries.  It's been
a while since I've been in that part of the code.]

Michael L. Hitch
Computer Consultant
Information Technology Center
Montana State University	Bozeman, MT	USA